ARM and Synopsys Reduce Time-to-Market for ARM Core-Based Designs; Collaboration Results in Complete RTL to GDSII Reference Design Flow

CAMBRIDGE, England and MOUNTAIN VIEW, Calif., Nov. 19 /PRNewswire/ -- ARM [(LSE: ARM); (Nasdaq: ARMHY - news)], the industry's leading provider of 16/32-bit embedded RISC microprocessor solutions, and Synopsys, Inc. (Nasdaq: SNPS - news), the technology leader for complex IC designs, today announced a jointly-developed reference design flow that streamlines the methodology used by ARM Partners to port ARM® microprocessor cores to their process technologies. The register transfer level (RTL) to GDSII reference design flow shortens time-to-market for ARM core-based designs. The fully integrated reference design flow is initially available for the ARM946E-S(TM) synthesizable microprocessor core and provides for the customization, re-implementation, re-verification and characterization of the core by leveraging Synopsys' advanced EDA technology.

"Providing a superior reference design flow is strategic to our business. When we enable Partners to do their own porting starting from synthesizable ARM cores, we must provide proven methods for retaining compliance with our architecture in their porting process," said Simon Segars, vice president, Engineering, ARM. "This new flow not only ensures architectural integrity, but it has significantly reduced implementation time on early core hardenings. This gives our Partners a significant market advantage. The reference design flow will become the foundation methodology for our soft IP core solution."

"The new reference design flow allows us to take the ARM946E-S core in RTL, re-implement it very quickly to our process and get a deterministically accurate, architecturally-compliant hardened core," said Luciano Raimondi, application specific DSP/ARM cores design manager of STMicroelectronics' TPA Groups. "We successfully evaluated the timing model extraction portion of the flow this summer and we are now introducing this flow in our sign-off procedure for use in future ARM projects."

The flow provides a predictable route to silicon using both logical and physical synthesis technologies and allows rapid technology and application- specific implementations of ARM cores optimized for performance, area and power. All necessary design views of the physical implementation are created to enable the rapid integration of the ARM core into a system-on-chip (SoC) design. The initial release of the flow includes Synopsys' Physical Compiler, Chip Architect, Design Compiler(TM), DC Ultra(TM), DesignWare®, Power Compiler(TM), Formality®, DFT Compiler, TetraMAX®, PrimeTime® and VCS(TM). The reference design flow is modular and based on standard interfaces allowing for the integration of complementary tools.

The reference flow is the first result of an ongoing collaboration between Synopsys and ARM. "ARM and Synopsys developed a reference design flow that enables ARM Partners to easily characterize and create all necessary design views of their own implementation," said Rich Goldman, vice president of Strategic Market Development for Synopsys. "This approach not only serves ARM's direct Partners, but end designers of ARM Powered® products can more rapidly integrate an ARM core into their products using the new reference design flow."

Availability

The ARM-Synopsys RTL to GDSII reference design flow will be available in November 2001 to ARM Partners as an Implementation Guide for the ARM946E-S microprocessor core, along with supporting scripts. For more information on the ARM-Synopsys reference design flow and to access the joint white paper, Soft IP Deployment: Creating and Integrating Virtual Components, contact: www.arm.com or www.synopsys.com .

About ARM

ARM is the industry's leading provider of 16/32-bit embedded RISC microprocessor solutions. The company licenses its high-performance, low-cost, power-efficient RISC processors, peripherals and system-on-chip designs to leading international electronics companies. ARM also provides comprehensive support required in developing a complete system. ARM's microprocessor cores are rapidly becoming the volume RISC standard in such markets as portable communications, hand-held computing, multimedia digital consumer and embedded solutions. More information on ARM is available at www.arm.com .

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS - news), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com .

ARM and ARM Powered are registered trademarks of ARM Limited. ARM946E-S is a trademark of ARM Limited. All other brands or product names are the property of their respective holders. "ARM" is used to represent ARM Holdings plc (LSE: ARM and Nasdaq: ARMHY); its operating company ARM Limited; and the regional subsidiaries ARM INC.; ARM KK; ARM Korea Ltd.; ARM Taiwan; and ARM France SAS.

Synopsys, DesignWare, Formality, TetraMAX and PrimeTime are registered trademarks of Synopsys, Inc. Design Compiler, DC Ultra, Power Compiler and VCS are trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

For further information, please contact Michelle Spencer of ARM, +1 44 1628 427780, michelle.spencer@arm.com; or Patrick Hall of The Townsend Agency, +1-858-457-4888 ext. 112, phall@townsendagency.com, for ARM; or Isela Gamboa of Synopsys, Inc., +1-650-584-1644, igamboa@synopsys.com; or Darren Ballegeer of Edelman Public Relations, +1-650-429-2735, darren.ballegeer@edelman.com, for Synopsys.